The present invention relates to integrated circuits, and in particular to isolation stress reduction in integrated circuits.
Field oxide layers electrically isolate semiconductor devices from one another. The most common technique for their formation is termed LOCOS isolation (for LOCal Oxidation of Silicon). Silicon dioxide (SiO2) is formed on silicon surfaces through a process termed oxidation. In the formation of field oxides, SiO2, is thermally grown to thicknesses of between 2,000 to 10,000 angstroms. Usually, oxidation is accomplished by exposing the silicon to an oxidant ambient, such as oxygen (O2) or water (H2O), at elevated temperatures. Oxide is formed on those areas which are not covered by an oxidation mask, such as silicon nitride.
The silicon nitride is deposited by chemical vapor deposition (CVD), and photolithographically patterned to form the oxidation mask, using a dry etch. Silicon nitride is an effective mask due to the slow speed with which oxygen and water vapor diffuse in the nitride (typically only a few tens of nanometers of nitride are converted to SiO2 during the field oxide growth process). Therefore, the nitride layer thickness is selected according to the time needed for the field oxidation step. Typically, the nitride masking layer is deposited to a thickness of between 500 and 3,000 angstroms. After field oxidation, the masking layer is removed by a wet etch for subsequent device formation in the regions previously under the mask Typically, the silicon nitride is formed on another oxide layer, typically called pad oxide. The pad oxide is formed on the silicon by thermal oxidation.
The silicon nitride is susceptible to intrinsic and extrinsic stress. Due to its stoichiometry, silicon nitride formed by low pressure CVD (LPCVD) has a high inherent tensile stress. However, encroachment by the field oxide, commonly referred to as the xe2x80x9cbird""s beakxe2x80x9d, into the silicon nitride also creates an extrinsic mechanical stress that increases the overall stress of the silicon nitride. As a result of its high stress, the silicon nitride deforms the periodic lattice of the silicon. Hence, dislocations are created in the silicon which give rise to undesired leakage currents. Thus, for example, in dynamic random access memories (DRAMs), the leakage currents necessitate an increased refresh rate. Therefore, the maximum frequency of read and write operations of the DRAM are reduced because refreshes must occur more often.
Previously, process techniques, such as forming oxide-nitride-oxide polysilicon buffer layers on the silicon, have been attempted to reduce the undesirable leakage currents. However, these techniques have proven unsatisfactory because they entail complex processing steps, and can create additional dislocations. Therefore, there remains a need to diminish the dislocations in the silicon caused by the silicon nitride.
Stress caused by a silicon nitride mask is diminished by forming the mask with a graded silicon concentration. Grading is accomplished by changing the silicon content in the silicon nitride by varying the amount of hydride, such as dichlorosilane (DCS), mixed with ammonia during oxidation to form the mask. The silicon nitride is graded in a substantially linear or non-linear fashion to vary the silicon nitride stress between compressive and tensile modes to reduce stress.
In one embodiment, the graded silicon nitride may be formed by an abrupt discontinuity, or junction, in the silicon concentration. The abrupt junction is created by forming a second silicon nitride layer on a first silicon nitride layer. The first and second silicon nitride layers have different concentrations of silicon.
In other embodiments, the stress caused by the xe2x80x9cbird""s beakxe2x80x9d can be reduced by forming the silicon nitride in a variety of shapes. The shape of silicon nitride can be fashioned during or after silicon nitride growth. The shape of the silicon nitride can be fashioned after the silicon nitride has been grown, for example, by etching.
In one embodiment, the stress from the silicon nitride is reduced by forming a buffer layer between two silicon nitride layers. The buffer layer may be polysilicon.
An additional benefit of the present invention is that the encroachment of the xe2x80x9cbird""s beakxe2x80x9d into the silicon nitride is decreased or not significantly increased by the aforementioned techniques. As a result, device leakage currents are diminished, while device gain and current capacity is not reduced. Further features and advantages of the present invention, as well as the structure and operation of recent embodiments of the present invention, are described in detail below with reference to the accompanying drawings.